Physical vapor deposition (PVD) is a frequently used processing technique in the manufacture of semiconductor wafers that involves the deposition of a metallic layer on the surface of a silicon wafer. It is also known as sputtering. In recently developed advanced semiconductor devices, PVD is frequently used to deposit metallic layers of Ti for contacts and metallic layers of Al for interconnects. PVD can also be used to deposit TiN as a barrier layer on silicon wafers.
In a PVD process, inert gas particles are first ionized in an electric field to produce a gas plasma. The ionized particles are then directed toward a source or target where the energy of these gas particles physically dislodges, or sputters off, atoms of the metallic source material. PVD is a versatile technique in that many materials can be deposited using not only RF but also DC power sources.
In a typical PVD process chamber, major components include a stainless steel chamber that is certified vacuum-tight with a helium leak detector, a pumping capacity that is capable of reducing the chamber pressure to about 10.sup.-6 Torr or below, pressure gauges, a sputter source or target, a power supply, and a wafer holder. The sputter source and the wafer holder are normally positioned facing each other. The target is, for example, an Al or Ti disc used as the sputter source for the process. The target has different sizes, for instance, a 13-inch (330 mm) target is normally used for processing 8-inch (200 mm) wafers. The target is bonded to a backing plate and has a life expectancy depending on the power consumption of the process and the target material used.
In recent years, more stringent requirements of film quality and increasing wafer sizes have driven the manufacturing technology away from very large batch systems toward single-wafer processing systems. Many integrated process systems that combine several process technologies in a single machine are becoming available in the market place. In such integrated process systems, a wafer can be transported from one single-wafer process chamber or module to another through a central transfer chamber without breaking vacuum. Consequently, many of the modem processing equipment are being designed for single-wafer use in multichamber clustered integrated processing systems.
In a typical multichamber clustered integrated processing system for PVD, thin or thick metal or barrier metal films can be deposited on silicon wafers of various sizes. For instance, four PVD process chambers can be connected to a transfer chamber which is then connected to other chambers such as a pre-clean chamber, a cool down chamber, a buffer chamber for a wafer handling, and a load-lock.
Anti-reflective coatings are frequently used in semiconductor processing to reduce light reflectance on the surface of metallic layers. For instance, they are frequently used on Al metallization layers which are deposited on wafers for interconnects. Aluminum is a widely used metallization layer material in semiconductor processing due to its low melting point, high conductivity and low cost. However, one drawback of Al is that the surface of Al is highly reflective. This high surface reflectivity greatly hampers the imaging process necessary for lithography. During a lithographic process, a photoresist layer must be deposited on the Al surface based on a photographical pattern previously formed in a photo-imaging mask. The high reflectivity from the surface of Al renders this photographic transfer process extremely difficult.
To reduce the high reflectivity of Al, an anti-reflective coating layer of TiN can be deposited on the surface of Al. The TiN layer appears as a brown or golden tint which significantly reduces the reflectivity of Al from near 100% to approximately 20% at the wavelengths of visible light. This anti-reflective coating deposition process is a very important step in semiconductor processes whenever a highly reflective metal layer is used.
For a deposition process of an anti-reflective coating (or ARC) on a silicon wafer, a typical stack arrangement on the silicon surface includes a Ti contact layer, a TiN barrier layer, an Al interconnect layer, and a TiN layer for the purpose of reducing optical reflection. A four PVD chamber cluster system can be ideally utilized in this deposition process by installing Ti targets in three chambers and Al target in one chamber. The Ti contact layer is deposited by maintaining a partial pressure of Ar gas in the chamber, while the TiN layers are deposited by maintaining a partial pressure of Ar and N.sub.2 gases in the process chamber. The Ar supports a plasma used in plasma sputtering while the N.sub.2 reacts with the sputtered Ti to form TiN.
In many industrial applications, there may Dot be four process chambers available for a TiN anti-reflective coating process. For instance, it may be desirable for economic reasons to perform an ARC process in only two process chambers. In such a case, a Ti target is used in one chamber and an Al target is used in the other chamber.
When only two PVD process chambers are used to fabricate a typical four-layer stack having a TiN anti-reflective coating, a silicon wafer is first coated in the Ti chamber with a Ti layer by flowing Ar gas in the chamber. The wafer while staying in the same chamber is then coated with a layer of TiN by flowing both Ar and N.sub.2 in the chamber. The silicon wafer is then transferred to the Al process chamber for the addition of the Al interconnect layer. After the Al deposition process, the wafer is transferred back to the Ti process chamber for the TiN anti-reflective coating process. This last step of TiN coating leaves a thin layer of TiN on the surface of the Ti target. Thereafter, the Al interconnect and Ti contact layers are photolithographically patterned into the desired contacts and interconnects.
When processing a second silicon wafer in the same process chamber, during the first deposition step where a pure Ti layer is supposed to be deposited on the silicon wafer, a thin layer of TiN is instead first deposited on the silicon surface resulting from the contaminated surface of the Ti target. This unwanted TiN layer at the interface of Ti and the underlying silicon greatly increases the contact resistance between them and reduces the efficiency of the Ti contact layer.
The problem of TiN contamination of a Ti target in a two-chamber system can be explained in more detail as follows. Referring initially to FIG. 1A, cross-sectional views of a Ti target 10 and a silicon wafer 20 are shown. The wafer 20 may have been previously partially processed into an integrated circuit. To process the first wafer 20, a layer 12 of Ti (i.e. a contact layer) is first deposited by flowing inert Ar gas through the process chamber. This is shown as step 1. Target 10 has a clean Ti surface after this first deposition step.
In the second deposition step for wafer 20, as shown in FIG. 1B, Ar and N.sub.2 are flowed through the process chamber forming layer 14 of TiN on top of the Ti layer 12. It is noted that after this deposition step, a thin layer 16 of TiN is left on the target surface 30. This TiN layer 16 contaminates the Ti target 10. The thickness of layer 16 shown in FIG. 1B can be of any thickness up to 20 nm.
In the processing of the second wafer 40, as shown in FIG. 2A, in the first step of deposition when Ar gas is flowed through the process chamber, the contaminant TiN layer 16 on target surface 30 is first deposited on wafer 40 as TiN layer 24. It should be emphasized that the TiN material in layer 16 shown in FIG. 1B on the target 10 is now deposited on the second wafer 40 as layer 24. After the brief deposition of TiN layer 24, an intended Ti layer 26 is then deposited on top of the TiN layer 24. In the second deposition step, shown in FIG. 2B, a layer of TiN is deposited on second wafer 40 by flowing Ar and N.sub.2 through the chamber to form the new TiN layer 28 on top of Ti layer 26. At the same time, another contaminant layer 32 of TiN is formed on the top surface 30 of the Ti target 10. The thickness of layer 32 can be of any thickness up to 20 nm. This starts another cycle of contamination for the next wafer to be processed in the same process chamber which also results in the undesired structure of FIG. 2B.
Others have proposed a solution to this problem of TiN contamination at the interface by placing a shutter at a position near the wafer. The unwanted TiN is then deposited on the shutter prior to the deposition of Ti on the silicon wafer. While this technique works in some application, many processing chambers do not allow the positioning of such a shutter near the wafer due to hardware configurations.
It is therefore an object of the present invention to provide a method of in-situ cleaning a Ti target without the necessity of using a shutter.
It is another object of the present invention to provide a method of in-situ cleaning a Ti target used in a TiN coating process without any modification to the processing chamber and equipment.
It is yet another object of the present invention to provide a method of in-situ cleaning a Ti target in a TiN anti-reflective coating process that can be performed in a simple processing step.
It is a further object of the present invention to provide a method of in-situ cleaning a Ti target in a TiN anti-reflective coating process by the addition of a thin Ti layer on top of the TiN layer while maintaining the desirable anti-reflective characteristic of the TiN layer.